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IC41C4405x and IC41LV4405x Series Document Title 4Mx4 bit Dynamic RAM with Fast Page Mode Revision History Revision No 0A 0B History Initial Draft add Industrial grade parts Draft Date June 10,2001 October 17,2002 Remark Preliminary The attached datasheets are provided by ICSI. Integrated Circuit Solution Inc reserve the right to change the specifications and products. ICSI will answer to your questions about device. If you have any questions, please contact the ICSI offices. Integrated Circuit Solution Inc. DR013-0B 10/17/2002 1 IC41C4405x and IC41LV4405x Series 4M x 4 (16-MBIT) DYNAMIC RAM WITH FAST PAGE MODE FEATURES * Fast Page Mode Access Cycle * TTL compatible inputs and outputs * Refresh Interval: -- 2,048 cycles/32 ms -- 4,096 cycles/64 ms * Refresh Mode: RAS-Only, CAS-before-RAS (CBR), and Hidden * JEDEC standard pinout * Single power supply: 5V 10% or 3.3V 10% * Byte Write and Byte Read operation via two CAS DESCRIPTION The ICSI 4405x Series is a 4,194,304 x 4-bit high-performance CMOS Dynamic Random Access Memory. The Fast Page Mode allows 2,048 or 4096 random accesses within a single row with access cycle time as short as 20 ns per 4-bit word. These features make the 4405x Series ideally suited for highbandwidth graphics, digital signal processing, high-performance computing systems, and peripheral applications. The 4405x Series is packaged in a 24-pin 300mil SOJ and a 24 pin TSOP-2 PRODUCT SERIES OVERVIEW Part No. IS41C44052 IS41C44054 IS41LV44052 IS41LV44054 2K 4K Refresh 2K 4K Voltage V10% 5 V10% 5 3.3V 10% 3.3V 10% KEY TIMING PARAMETERS Parameter RAS Access Time (tRAC) CAS Access Time (tCAC) Column Address Access Time (tAA) Fast Page Mode Cycle Time (tPC) Read/Write Cycle Time (tRC) -50 0 5 1 3 2 5 2 0 8 4 6 0 15 30 25 104 -60 ns ns ns ns ns Unit PIN CONFIGURATION 24 (26) Pin SOJ, TSOP-2 VCC I/O0 I/O1 WE RAS *A11(NC) A10 A0 A1 A2 A3 VCC 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 GND I/O3 I/O2 CAS OE A9 A8 A7 A6 A5 A4 GND PIN DESCRIPTIONS A0-A11 A0-A10 I/O0-3 WE OE RAS CAS Vc c GND NC Address Inputs (4K Refresh) Address Inputs (2K Refresh) Data Inputs/Outputs Write Enable Output Enable Row Address Strobe Column Address Strobe Power Ground No Connection * A11 is NC for 2K Refresh devices. ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors which may appear in this publication. (c) Copyright 2000, Integrated Circuit Solution Inc. 2 Integrated Circuit Solution Inc. DR013-0B 10/17/2002 IC41C4405x and IC41LV4405x Series FUNCTIONAL BLOCK DIAGRAM OE WE CAS CONTROL LOGIC WE CONTROL LOGICS OE CONTROL LOGIC OE CAS CAS WE RAS RAS CLOCK GENERATOR DATA I/O BUS REFRESH COUNTER DATA I/O BUFFERS ROW DECODER RAS COLUMN DECODERS SENSE AMPLIFIERS I/O0-I/O3 MEMORY ARRAY 4,194,304 x 4 ADDRESS BUFFERS A0-A10(A11) TRUTH TABLE Function Standby Read Write: Word (Early Write) Read-Write Hidden Refresh RAS-Only Refresh CBR Refresh Note: 1. EARLY WRITE only. Read Write(1) RAS H L L L LHL LHL L HL CAS H L L L L L H L WE X H L HL H L X X OE X L X LH L X X X Address tR/tC X ROW/COL ROW/COL ROW/COL ROW/COL ROW/COL ROW/NA X I/O High-Z DOUT DIN DOUT, DIN DOUT DOUT High-Z High-Z Integrated Circuit Solution Inc. DR013-0B 10/17/2002 3 IC41C4405x and IC41LV4405x Series Functional Description The IC41C4405x and IC41LV4405x are CMOS DRAMs optimized for high-speed bandwidth, low power applications. During READ or WRITE cycles, each bit is uniquely addressed through the 11 or 12 address bits. These are entered 11 bits (A0-A10) at a time for the 2K refresh device or 12 bits (A0-A11) at a time for the 4K refresh device. The row address is latched by the Row Address Strobe (RAS). The column address is latched by the Column Address Strobe (CAS). RAS is used to latch the first nine bits and CAS is used the latter ten bits. Refresh Cycle To retain data, 2,048 refresh cycles are required in each 32 ms period, or 4,096 refresh cycles are required in each 64ms period. There are two ways to refresh the memory: 1. By clocking each of the 2,048 row addresses (A0 through A10) or 4096 row addresses (A0 through A11) with RAS at least once every 32 ms or 64ms respectively. Any read, write, read-modify-write or RAS-only cycle refreshes the addressed row. 2. Using a CAS-before-RAS refresh cycle. CAS-beforeRAS refresh is activated by the falling edge of RAS, while holding CAS LOW. In CAS-before-RAS refresh cycle, an internal 11(12)-bit counter provides the row addresses and the external address inputs are ignored. CAS-before-RAS is a refresh-only mode and no data access or device selection is allowed. Thus, the output remains in the High-Z state during the cycle. Memory Cycle A memory cycle is initiated by bring RAS LOW and it is terminated by returning both RAS and CAS HIGH. To ensures proper device operation and data integrity any memory cycle, once initiated, must not be ended or aborted before the minimum tRAS time has expired. A new cycle must not be initiated until the minimum precharge time tRP, tCP has elapsed. Power-On After application of the VCC supply, an initial pause of 200 s is required followed by a minimum of eight initialization cycles (any combination of cycles containing a RAS signal). During power-on, it is recommended that RAS track with VCC or be held at a valid VIH to avoid current surges. Read Cycle A read cycle is initiated by the falling edge of CAS or OE, whichever occurs last, while holding WE HIGH. The column address must be held for a minimum time specified by tAR. Data Out becomes valid only when tRAC, tAA, tCAC and tOEA are all satisfied. As a result, the access time is dependent on the timing relationships between these parameters. Write Cycle A write cycle is initiated by the falling edge of CAS and WE, whichever occurs last. The input data must be valid at or before the falling edge of CAS or WE, whichever occurs last. 4 Integrated Circuit Solution Inc. DR013-0B 10/17/2002 IC41C4405x and IC41LV4405x Series ABSOLUTE MAXIMUM RATINGS(1) Symbol VT VCC IOUT PD TA TSTG Parameters Voltage on Any Pin Relative to GND Supply Voltage Output Current Power Dissipation Commercial Operation Temperature Industrial Operation Temperature Storage Temperature 5V 3.3V 5V 3.3V Rating -1.0 to +7.0 -0.5 to +4.6 -1.0 to +7.0 -0.5 to +4.6 50 1 0 to +70 -40 to +85 -55 to +125 Unit V V mA W o C o C o C Note: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. RECOMMENDED OPERATING CONDITIONS (Voltages are referenced to GND.) Symbol VCC VIH VIL TA Parameter Supply Voltage Input High Voltage Input Low Voltage Commercial Ambient Temperature Industrial Operation Temperature 5V 3.3V 5V 3.3V 5V 3.3V Min. 4.5 3.0 2.4 2.0 -1.0 -0.3 0 -40 Typ. 5.0 3.3 - - - - - - Max. 5.5 3.6 VCC + 1.0 VCC + 0.3 0.8 0.8 70 85 Unit V V V o o C C CAPACITANCE(1,2) Symbol CIN1 CIN2 CIO Parameter Input Capacitance: A0-A10(A11) Input Capacitance: RAS, CAS, WE, OE Data Input/Output Capacitance: I/O0-I/O3 Max. 5 7 7 Unit pF pF pF Notes: 1. Tested initially and after any design or process changes that may affect these parameters. 2. Test conditions: TA = 25oC, f = 1 MHz. Integrated Circuit Solution Inc. DR013-0B 10/17/2002 5 IC41C4405x and IC41LV4405x Series ELECTRICAL CHARACTERISTICS(1) (Recommended Operating Conditions unless otherwise noted.) Symbol IIL IIO VOH VOL ICC1 ICC2 ICC3 Parameter Input Leakage Current Output Leakage Current Output High Voltage Level Output Low Voltage Level Standby Current: TTL Standby Current: CMOS Operating Current: Random Read/Write(2,3,4) Average Power Supply Current Operating Current: Fast Page Mode(2,3,4) Average Power Supply Current Refresh Current: RAS-Only(2,3) Average Power Supply Current Refresh Current: CBR(2,3,5) Average Power Supply Current Test Condition Any input 0V < VIN < Vcc Other inputs not under test = 0V Output is disabled (Hi-Z) 0V < VOUT < Vcc IOH = -5.0 mA with VCC=5V IOH = -2.0 mA with VCC=3.3V IOL = 4.2 mA with VCC=5V IOL = 2 mA with VCC=3.3V RAS, CAS - VIH RAS, CAS > VCC - 0.2V RAS, CAS, Address Cycling, tRC = tRC (min.) RAS = VIL, CAS > VIH tRC = tRC (min.) RAS Cycling, CAS > VIH tRC = tRC (min.) RAS, CAS Cycling tRC = tRC (min.) 5V 3.3V 5V 3.3V -50 -60 -50 -60 -50 -60 -50 -60 Speed Min. -5 -5 2.4 - - - - - - - - - - - - - Max. 5 5 - 0.4 2 0.5 1 0.5 120 110 90 80 120 110 120 110 Unit A A V V mA mA mA ICC4 mA ICC5 mA ICC6 mA Notes: 1. An initial pause of 200 s is required after power-up followed by eight RAS refresh cycles (RAS-Only or CBR) before proper device operation is assured. The eight RAS cycles wake-up should be repeated any time the tREF refresh requirement is exceeded. 2. Dependent on cycle rates. 3. Specified values are obtained with minimum cycle time and the output open. 4. Column-address is changed once each Fast page cycle. 5. Enables on-chip refresh and address counters. 6 Integrated Circuit Solution Inc. DR013-0B 10/17/2002 IC41C4405x and IC41LV4405x Series AC CHARACTERISTICS(1,2,3,4,5,6) (Recommended Operating Conditions unless otherwise noted.) Symbol tRC tRAC tCAC tAA tRAS tRP tCAS tCP tCSH tRCD tASR tRAH tASC tCAH tAR tRAD tRAL tRPC tRSH tRHCP tCLZ tCRP tOD tOE tOED tOEHC tOEP tOES tRCS tRRH tRCH tWCH tWCR tWP tWPZ tRWL tCWL tWCS tDHR Parameter Random READ or WRITE Cycle Time Access Time from RAS(6, 7) Access Time from CAS(6, 8, 15) Access Time from Column-Address(6) RAS Pulse Width RAS Precharge Time CAS Pulse Width(23) CAS Precharge Time(9) CAS Hold Time (21) RAS to CAS Delay Time(10, 20) Row-Address Setup Time Row-Address Hold Time Column-Address Setup Time(20) Column-Address Hold Time(20) Column-Address Hold Time (referenced to RAS) RAS to Column-Address Delay Time(11) Column-Address to RAS Lead Time RAS to CAS Precharge Time RAS Hold Time RAS Hold Time from CAS Precharge CAS to Output in Low-Z(15, 24) CAS to RAS Precharge Time(21) Output Disable Time(19, 24) Output Enable Time(15, 16) Output Enable Data Delay (Write) OE HIGH Hold Time from CAS HIGH OE HIGH Pulse Width OE LOW to CAS HIGH Setup Time Read Command Setup Time(17, 20) Read Command Hold Time (referenced to RAS)(12) Read Command Hold Time (referenced to CAS)(12, 17, 21) Write Command Hold Time(17) Write Command Hold Time (referenced to RAS)(17) Write Command Pulse Width(17) WE Pulse Widths to Disable Outputs Write Command to RAS Lead Time(17) Write Command to CAS Lead Time(17, 21) Write Command Setup Time(14, 17, 20) Data-in Hold Time (referenced to RAS) Min. 84 - - - 50 30 8 9 38 12 0 8 0 8 30 10 25 5 8 30 0 5 3 - 12 5 10 5 0 0 0 8 40 8 7 13 8 0 39 -50 Max. - 50 13 25 10K - 10K - - 37 - - - - - 25 - - - - - - 15 12 - - - - - - - - - - - - - - - Min. 104 - - - 60 40 10 9 40 14 0 10 0 10 40 12 30 5 10 35 0 5 3 - 15 5 10 5 0 0 0 10 50 10 7 15 10 0 39 -60 Max. - 60 15 30 10K - 10K - - 45 - - - - - 30 - - - - - - 15 15 - - - - - - - - - - - - - - - Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 7 Integrated Circuit Solution Inc. DR013-0B 10/17/2002 IC41C4405x and IC41LV4405x Series AC CHARACTERISTICS (Continued)(1,2,3,4,5,6) (Recommended Operating Conditions unless otherwise noted.) Symbol tACH tOEH tDS tDH tRWC tRWD tCWD tAWD tPC tRASP tCPA tPRWC tCOH tOFF tWHZ tCSR tCHR tORD tREF tT Parameter Column-Address Setup Time to CAS Precharge during WRITE Cycle OE Hold Time from WE during READ-MODIFY-WRITE cycle(18) Data-In Setup Time(15, 22) Data-In Hold Time(15, 22) READ-MODIFY-WRITE Cycle Time RAS to WE Delay Time during READ-MODIFY-WRITE Cycle(14) CAS to WE Delay Time(14, 20) Column-Address to WE Delay Time(14) Fast Page Mode READ or WRITE Cycle Time RAS Pulse Width Access Time from CAS Precharge(15) READ-WRITE Cycle Time Data Output Hold after CAS LOW Output Buffer Turn-Off Delay from CAS or RAS(13,15,19, 24) Output Disable Delay from WE CAS Setup Time (CBR REFRESH)(20, 25) CAS Hold Time (CBR REFRESH)( 21, 25) OE Setup Time prior to RAS during HIDDEN REFRESH Cycle Auto Refresh Period 2,048 Cycles 4,096 Cycles Transition Time (Rise or Fall)(2, 3) Min. 15 8 0 8 108 64 26 39 20 50 - 56 5 0 3 5 8 0 - - 1 -50 Max. - - - - - - - - - 100K 30 - - 12 10 - - - 32 64 50 Min. 15 10 0 10 133 77 32 47 25 60 - 68 5 0 3 5 10 0 - - 1 -60 Max. - - - - - - - - - 100K 35 - - 15 10 - - - 32 64 50 Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms ns AC TEST CONDITIONS Output load: Two TTL Loads and 50 pF (Vcc = 5.0V + 10%) One TTL Load and 50 pF (Vcc = 3.3V + 10%) VIH = 2.4V, VIL = 0.8V (Vcc = 5.0V + 10%) VIH = 2.4V, VIL = 0.8V (Vcc = 3.3V + 10%) Input timing reference levels: Output timing reference levels: VOH = 2.0V, VOL = 0.8V (Vcc = 5.0V + 10%, 3.3V + 10%) 8 Integrated Circuit Solution Inc. DR013-0B 10/17/2002 IC41C4405x and IC41LV4405x Series Notes: 1. An initial pause of 200 s is required after power-up followed by eight RAS refresh cycle (RAS-Only or CBR) before proper device operation is assured. The eight RAS cycles wake-up should be repeated any time the tREF refresh requirement is exceeded. 2. VIH (MIN) and VIL (MAX) are reference levels for measuring timing of input signals. Transition times, are measured between VIH and VIL (or between VIL and VIH) and assume to be 1 ns for all inputs. 3. In addition to meeting the transition rate specification, all input signals must transit between VIH and VIL (or between VIL and VIH) in a monotonic manner. 4. If CAS and RAS = VIH, data output is High-Z. 5. If CAS = VIL, data output may contain data from the last valid READ cycle. 6. Measured with a load equivalent to one TTL gate and 50 pF. 7. Assumes that tRCD < tRCD (MAX). If tRCD is greater than the maximum recommended value shown in this table, tRAC will increase by the amount that tRCD exceeds the value shown. 8. Assumes that tRCD > tRCD (MAX). 9. If CAS is LOW at the falling edge of RAS, data out will be maintained from the previous cycle. To initiate a new cycle and clear the data output buffer, CAS and RAS must be pulsed for tCP. 10. Operation with the tRCD (MAX) limit ensures that tRAC (MAX) can be met. tRCD (MAX) is specified as a reference point only; if tRCD is greater than the specified tRCD (MAX) limit, access time is controlled exclusively by tCAC. 11. Operation within the tRAD (MAX) limit ensures that tRCD (MAX) can be met. tRAD (MAX) is specified as a reference point only; if tRAD is greater than the specified tRAD (MAX) limit, access time is controlled exclusively by tAA. 12. Either tRCH or tRRH must be satisfied for a READ cycle. 13. tOFF (MAX) defines the time at which the output achieves the open circuit condition; it is not a reference to VOH or VOL. 14. tWCS, tRWD, tAWD and tCWD are restrictive operating parameters in LATE WRITE and READ-MODIFY-WRITE cycle only. If tWCS > tWCS (MIN), the cycle is an EARLY WRITE cycle and the data output will remain open circuit throughout the entire cycle. If tRWD > tRWD (MIN), tAWD > tAWD (MIN) and tCWD > tCWD (MIN), the cycle is a READ-WRITE cycle and the data output will contain data read from the selected cell. If neither of the above conditions is met, the state of I/O (at access time and until CAS and RAS or OE go back to VIH) is indeterminate. OE held HIGH and WE taken LOW after CAS goes LOW result in a LATE WRITE (OE-controlled) cycle. 15. Output parameter (I/O) is referenced to corresponding CAS input. 16. During a READ cycle, if OE is LOW then taken HIGH before CAS goes HIGH, I/O goes open. If OE is tied permanently LOW, a LATE WRITE or READ-MODIFY-WRITE is not possible. 17. Write command is defined as WE going low. 18. LATE WRITE and READ-MODIFY-WRITE cycles must have both tOD and tOEH met (OE HIGH during WRITE cycle) in order to ensure that the output buffers will be open during the WRITE cycle. The I/Os will provide the previously written data if CAS remains LOW and OE is taken back to LOW after tOEH is met. 19. The I/Os are in open during READ cycles once tOD or tOFF occur. 20. Determined by falling edge of CAS. 21. Determined by rising edge of CAS. 22. These parameters are referenced to CAS leading edge in EARLY WRITE cycles and WE leading edge in LATE WRITE or READMODIFY-WRITE cycles. 23. CAS must meet minimum pulse width. 24. The 3 ns minimum is a parameter guaranteed by design. 25. Enables on-chip refresh and address counters. Integrated Circuit Solution Inc. DR013-0B 10/17/2002 9 IC41C4405x and IC41LV4405x Series FAST-PAGE-MODE READ CYCLE tRC tRAS tRP RAS tCSH tCRP tRCD tRSH tCAS tCLCH tRRH CAS tAR tASR tRAD tRAH tRAL tASC tCAH ADDRESS WE Row tRCS Column tRCH Row tAA tRAC tCAC tCLC tOFF(1) I/O Open tOE Valid Data tOD Open OE tOES Don't Care 10 Integrated Circuit Solution Inc. DR013-0B 10/17/2002 IC41C4405x and IC41LV4405x Series FAST PAGE MODE READ-MODIFY-WRITE CYCLE tRASP tRP RAS tCSH tCAS tCRP tRCD tCP tPRWC tCAS tCP tRSH tCAS tCRP CAS tAR tRAH tASR tRAD tASC tCAH tCPWD tASC tAR tCWL tRWD tAWD tCWD tCAH tCPWD tRAL tCAH tASC ADDRESS Row Column Column tCWL tAWD tCWD Column tCWL tRWL tWP tAWD tCWD tRCS tWP tWP WE tAA tCAC tOE tCAC tOE tAA tCAC tOE tAA OE tOEZ tOED tDH tDS tCLZ OUT IN OUT IN tRAC tCLZ tOEZ tOED tDH tDS tCLZ OUT tOEZ tOED tDH tDS IN I/O Don't Care Integrated Circuit Solution Inc. DR013-0B 10/17/2002 11 IC41C4405x and IC41LV4405x Series FAST-PAGE-MODE EARLY WRITE CYCLE (OE = DON'T CARE) tRC tRAS tRP RAS tCSH tCRP tRCD tRSH tCAS tCLCH CAS tAR tASR tRAD tRAH tASC tRAL tCAH tACH ADDRESS Row Column tCWL tRWL tWCR tWCS tWCH tWP Row WE tDHR tDS tDH I/O Valid Data Don't Care 12 Integrated Circuit Solution Inc. DR013-0B 10/17/2002 IC41C4405x and IC41LV4405x Series FAST-PAGE-MODE READ WRITE CYCLE (LATE WRITE and READ-MODIFY-WRITE Cycles) tRWC tRAS tRP RAS tCSH tCRP tRCD tRSH tCAS tCLCH CAS tAR tASR tRAD tRAH tRAL tASC tCAH tACH ADDRESS Row tRCS Column tRWD tCWD tAWD Row tCWL tRWL tWP WE tAA tRAC tCAC tCLZ tDS tDH I/O Open tOE Valid DOUT tOD Valid DIN Open tOEH OE Don't Care Integrated Circuit Solution Inc. DR013-0B 10/17/2002 13 IC41C4405x and IC41LV4405x Series FAST PAGE MODE EARLY WRITE CYCLE tRASP tRP tRHCP tRSH tCAS tCP tCRP RAS tCSH tCAS tCRP tRCD tCP tPC tCAS CAS tAR tRAL tRAH tASR tRAD tASC tCAH tASC tAR tCWL tWCS tWP tWCH tWCS tWP tCAH tASC tCAH ADDRESS Row Column Column tCWL tWCH tWCS Column tCWL tWCH tWP WE tWCR OE tDHR tDS tDH tDS tDH tDS tDH I/O Valid DIN Valid DIN Valid DIN Don't Care 14 Integrated Circuit Solution Inc. DR013-0B 10/17/2002 IC41C4405x and IC41LV4405x Series AC WAVEFORMS READ CYCLE (With WE-Controlled Disable) RAS tCSH tCRP tRCD tCAS tCP CAS tAR tASR tRAD tRAH tASC tCAH tASC ADDRESS WE Row tRCS Column tRCH tRCS Column tAA tRAC tCAC tCLZ tWHZ tCLZ I/O Open tOE Valid Data Open tOD OE Don't Care RAS-ONLY REFRESH CYCLE (OE, WE = DON'T CARE) RAS tRC tRAS tRP RAS tCRP tRPC CAS tASR tRAH ADDRESS I/O Row Open Row Don't Care Integrated Circuit Solution Inc. DR013-0B 10/17/2002 15 IC41C4405x and IC41LV4405x Series CBR REFRESH CYCLE (Addresses; WE, OE = DON'T CARE) tRP tRAS tRP tRAS RAS tRPC tCP tCHR tCSR tRPC tCSR tCHR CAS I/O Open Don't Care HIDDEN REFRESH CYCLE(1) (WE = HIGH; OE = LOW) tRAS tRP tRAS RAS tCRP tRCD tRSH tCHR CAS tAR tASR tRAD tRAH tASC tRAL tCAH ADDRESS Row Column tAA tRAC tCAC tCLZ tOFF(2) I/O Open tOE tORD Valid Data Open tOD OE Don't Care 16 Integrated Circuit Solution Inc. DR013-0B 10/17/2002 IC41C4405x and IC41LV4405x Series ORDERING INFORMATION Commercial Range: 0C to 70C Voltage: 5V Speed (ns) 50 50 60 60 Order Part No. IC41C44052-50J IC41C44052-50T IC41C44052-60J IC41C44052-60T Refresh 2K 2K 2K 2K Package 300mil SOJ 300mil TSOP-2 300-mil SOJ 300mil TSOP-2 Speed (ns) 50 50 60 60 Order Part No. IC41C44054-50J IC41C44054-50T IC41C44054-60J IC41C44054-60T Refresh 4K 4K 4K 4K Package 300mil SOJ 300mil TSOP-2 300mil SOJ 300mil TSOP-2 Voltage: 3.3V Speed (ns) 50 50 60 60 Order Part No. IC41LV44052-50J IC41LV44052-50T IC41LV44052-60J IC41LV44052-60T Refresh 2K 2K 2K 2K Package 300mil SOJ 300mil TSOP-2 300mil SOJ 300mil TSOP-2 Speed (ns) 50 50 60 60 Order Part No. IC41LV44054-50J IC41LV44054-50T IC41LV44054-60J IC41LV44054-60T Refresh 4K 4K 4K 4K Package 300mil SOJ 300mil TSOP-2 300mil SOJ 300mil TSOP-2 Integrated Circuit Solution Inc. HEADQUARTER: NO.2, TECHNOLOGY RD. V, SCIENCE-BASED INDUSTRIAL PARK, HSIN-CHU, TAIWAN, R.O.C. TEL: 886-3-5780333 Fax: 886-3-5783000 BRANCH OFFICE: 7F, NO. 106, SEC. 1, HSIN-TAI 5TH ROAD, HSICHIH TAIPEI COUNTY, TAIWAN, R.O.C. TEL: 886-2-26962140 FAX: 886-2-26962252 http://www.icsi.com.tw Integrated Circuit Solution Inc. DR013-0B 10/17/2002 17 IC41C4405x and IC41LV4405x Series ORDERING INFORMATION Industrial Range: -40C to 85C Voltage: 5V Speed (ns) 50 50 60 60 Order Part No. IC41C44052-50JI IC41C44052-50TI IC41C44052-60JI IC41C44052-60TI Refresh 2K 2K 2K 2K Package 300mil SOJ 300mil TSOP-2 300-mil SOJ 300mil TSOP-2 Speed (ns) 50 50 60 60 Order Part No. IC41C44054-50JI IC41C44054-50TI IC41C44054-60JI IC41C44054-60TI Refresh 4K 4K 4K 4K Package 300mil SOJ 300mil TSOP-2 300mil SOJ 300mil TSOP-2 Voltage: 3.3V Speed (ns) 50 50 60 60 Order Part No. IC41LV44052-50JI IC41LV44052-50TI IC41LV44052-60JI IC41LV44052-60TI Refresh 2K 2K 2K 2K Package 300mil SOJ 300mil TSOP-2 300mil SOJ 300mil TSOP-2 Speed (ns) 50 50 60 60 Order Part No. IC41LV44054-50JI IC41LV44054-50TI IC41LV44054-60JI IC41LV44054-60TI Refresh 4K 4K 4K 4K Package 300mil SOJ 300mil TSOP-2 300mil SOJ 300mil TSOP-2 Integrated Circuit Solution Inc. HEADQUARTER: NO.2, TECHNOLOGY RD. V, SCIENCE-BASED INDUSTRIAL PARK, HSIN-CHU, TAIWAN, R.O.C. TEL: 886-3-5780333 Fax: 886-3-5783000 BRANCH OFFICE: 7F, NO. 106, SEC. 1, HSIN-TAI 5TH ROAD, HSICHIH TAIPEI COUNTY, TAIWAN, R.O.C. TEL: 886-2-26962140 FAX: 886-2-26962252 http://www.icsi.com.tw 18 Integrated Circuit Solution Inc. DR013-0B 10/17/2002 |
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